The present invention relates to semiconductor transistors, and more particularly, to a method of making self aligned static induction transistors.
The prior art relating to static induction transistors are described in "Static Induction Transistors Optimized for High-Voltage Operation and High Microwave Power Output", by Izak Bencuya, et al., published in IEEE Transactions on Electron Devices, Vol. ED-32, No. 7, Jul. 1985, and "Effects of Shielded-Gate Structure on On-Resistance of the SIT with a High-Purity Channel Region", by Koji Yano, et al. published in IEEE Transactions on Electron Devices, Vol. ED-39, No. 5, Jul. 1992, for example. Prior art static induction transistors, such as those discussed in these references are not self aligned and are therefore slower for a given power and/or voltage level.
It is therefore an objective of the present invention to provide for a method of making self aligned static induction transistors.